1. Field of the Invention
The present invention relates to silicon carbide semiconductor devices.
2. Description of the Background Art
Conventionally, silicon has been widely used as a material for a semiconductor device. In recent years, silicon carbide has been increasingly employed as a material for a semiconductor device. Silicon carbide is a wide band gap semiconductor having a band gap wider than that of silicon. By employing silicon carbide as a material for a semiconductor device, a higher breakdown voltage and loss reduction of the semiconductor device can be achieved, and the semiconductor device can be used in a high-temperature environment.
In order to attain a higher breakdown voltage of a semiconductor device, the structure of a semiconductor device has been studied in addition to the material of a semiconductor device. As an example, a silicon carbide semiconductor device having an outer peripheral structure surrounding an outer periphery of a transistor cell region has been proposed.
For example, Japanese Patent Laying-Open No. 2013-38308 discloses a silicon carbide semiconductor device including a transistor cell region and an outer voltage-breakdown-resistant structure that surrounds an outer periphery of the transistor cell region. The outer voltage-breakdown-resistant structure includes a P type RESURF (Reduced Surface Field) layer. The P type RESURF layer includes a first P type region formed at the bottom of a first recess, a second P type region formed at the bottom of a second recess, and a P+ type layer connecting the first P type region and the second P type region to each other. The first recess is formed deeper than the second recess. The first P type region is provided on the P+ type layer forming a gate region of a transistor cell.
Japanese Patent Laying-Open No. 2010-225615 discloses a silicon carbide semiconductor device having a mesa structure portion formed in an outer peripheral region. The mesa structure portion includes a recess. A P type RESURF layer is formed at the bottom of the recess. The P type RESURF layer is connected to a P+ type contact layer. The P+ type contact layer is provided in a P type region forming a base region of a transistor.